Non-volatile memory devices such as flash memory devices do not lose data stored in their memory cells when the electric power supplied to the device is interrupted. Thus, the flash memory device is widely used in memory cards or the like. Flash memory devices are generally of two types: the NAND-type flash memory device and the NOR-type flash memory device.
A cell array region of the NAND-type flash memory device comprises a plurality of strings. The string typically includes a string selection transistor, a plurality of cell transistors and a ground selection transistor, which are serially connected. The drain region of the string selection transistor is connected to a bit line, and the source region of the ground selection transistor is connected to a common source line.
A cell array region of the NOR-type flash memory device contains a plurality of cell transistors, bit lines and common source lines. Here, only one cell transistor is electrically interposed between the bit line and the common source line.
Accordingly, the NAND-type flash memory device has higher integration density and smaller cell current as compared to the NOR-type flash memory device. The cell current corresponds to current flowing through the bit line and the common source line during a read mode. Thus, it is required to increase the cell current of the NAND-type flash memory device more so than it is in the NOR-type flash memory device. This is because the cell current directly affects access time of the flash memory device. As a result, it is required to decrease electrical resistance of the bit line and/or the common source line in order to improve the access time of the NAND-type flash memory device.
FIG. 1 is a top plan view showing a portion of cell array region of a conventional NAND-type flash memory device. Also, FIG. 2A is a cross-sectional view along the line I—I of FIG. 1, and FIG. 2B is a cross-sectional view along the line II—II of FIG. 1.
Referring to FIGS. 1, 2A and 2B, an isolation layer 1a defining a plurality of active regions 1 is formed at a predetermined region of a semiconductor substrate 10. The active regions 1 are defined in parallel to each other. A string selection line pattern 2s, first to nth word line patterns WP1 to WPn, and a ground selection line pattern 2g are formed across the isolation layer 1a and the active regions 1. Impurity regions 7, 7d and 7s are formed at the active regions 1 among the string selection line pattern 2s, the first to nth word line patterns WP1 to WPn, and the ground selection line pattern 2g. Here, the impurity region 7d formed at one side of the string selection line pattern 2s acts as a drain region of the string selection transistor. Also, the impurity region 7s formed at one side of the ground selection line pattern 2g acts as a source region of the ground selection transistor.
Accordingly, the string selection transistor is formed at a portion at which the string selection line pattern 2s and the active region 1 intersect each other. Similarly, the ground selection transistor is formed at a portion at which the ground selection line pattern 2g and the active region 1 intersect each other. Also, the cell transistors are formed at portions at which the word line patterns WP1 to WPn and the active region 1 intersect each other. As a result, a string is formed at each active region 1. Here, the string includes the string selection transistor, the cell transistors and the ground selection transistor that are serially connected.
A first interlayer insulating layer 4 is formed on the entire surface of the substrate including the strings. The first interlayer insulating layer 4 is patterned to form common source line contact holes 3 exposing the respective source regions 7s. A conductive layer filling the common source line contact holes 3, e.g., a doped polysilicon layer, is then formed on the first interlayer insulating layer 4. The conductive layer is patterned to form a common source line 5 covering the common source line contact holes 3. The common source line 5 is electrically connected to the source regions 7s through the common source line contact holes 3.
The common source line 5 and the first interlayer insulating layer 4 are covered with a second interlayer insulating layer 6. The second interlayer insulating layer 6 and the first interlayer insulating layer 4 are successively patterned to form bit line contact holes 8 exposing the respective drain regions 7d. Bit line contact plugs 8a are formed in the respective bit line contact holes 8. A metal layer is formed on the entire surface of the resultant structure where the bit line contact plugs 8a are formed. The metal layer is then patterned to form a plurality of bit lines 9 covering the respective bit line contact plugs 8a. The plurality of bit lines 9 cross over the first to nth word line patterns WP1 to WPn.
As described above, according to the conventional technology, the common source line is interposed between the first and second interlayer insulating layers. Thus, the thickness of the common source line should be increased in order to reduce the resistance of the common source line. However, in the event that the thickness of the common source line is increased, the thickness of the second interlayer insulating layer should be also increased in order to enhance the isolation characteristic between the bit lines and the common source line. At this time, the aspect ratio of the bit line contact holes penetrating the first and second interlayer insulating layers is increased. As a result, it is required to minimize the resistance of the common source line as well as the aspect ratio of the bit line contact holes.